Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsRAM_MODE => "TDP",-- SDP or TDPREAD_WIDTH_A => 0,-- 0, 1, 2, 4, 9, 18, or-- 36READ_WIDTH_B => 0, -- 0, 1, 2, 4, 9, 18RSTREG_PRIORITY_A => "RSTREG",-- RSTREG or REGCERSTREG_PRIORITY_B => "RSTREG",-- RSTREG or REGCESIM_COLLISION_CHECK => "ALL",-- Collision check-- enable "ALL",-- "WARNING_ONLY",-- "GENERATE_X_ONLY" or-- "NONE"SRVAL_A => X"0000000",-- Set/Reset value for A-- port outputSRVAL_B => X"0000000",-- Set/Reset value for B-- port outputWRITE_WIDTH_A => 0, -- 0, 1, 2, 4, 9, or 18WRITE_WIDTH_B => 0,-- 0, 1, 2, 4, 9, 18, or-- 36-- WriteMode: Specifies output behavior of the port being written to: "WRITE_FIRST" = written value-- appears on output port of the RAM "READ_FIRST" = previous RAM contents for that memory location appear-- on the output port "NO_CHANGE" = previous value on the output port remains the same. Default is-- WRITE_FIRST in TDP mode. Must equal READ_FIRST in SDP mode.WRITE_MODE_A => "WRITE_FIRST",WRITE_MODE_B => "WRITE_FIRST")port map (DOADO => DOADO,-- 16-bit A port data/LSB data outputDOBDO => DOBDO,-- 16-bit B port data/MSB data outputDOPADOP => DOPADOP,-- 2-bit A port parity/LSB parity outputDOPBDOP => DOPBDOP,-- 2-bit B port parity/MSB parity outputADDRARDADDR => ADDRARDADDR, -- 14-bit A port address/Read address inputADDRBWRADDR => ADDRBWRADDR, -- 14-bit B port address/Write address inputCLKARDCLK => CLKARDCLK,-- 1-bit A port clock/Read clock inputCLKBWRCLK => CLKBWRCLK,-- 1-bit B port clock/Write clock inputDIADI => DIADI,-- 16-bit A port data/LSB data inputDIBDI => DIBDI,-- 16-bit B port data/MSB data inputDIPADIP => DIPADIP,-- 2-bit A port parity/LSB parity inputDIPBDIP => DIPBDIP,-- 2-bit B port parity/MSB parity inputENARDEN => ENARDEN,-- 1-bit A port enable/Read enable inputENBWREN => ENBWREN,-- 1-bit B port enable/Write enable inputREGCEAREGCE => REGCEAREGCE, -- 1-bit A port register enable/Register enable inputREGCEB => REGCEB,-- 1-bit B port register enable inputRSTRAMARSTRAM => RSTRAMARSTRAM, -- 1-bit A port set/reset inputRSTRAMB => RSTRAMB,-- 1-bit B port set/reset inputRSTREGARSTREG => RSTREGARSTREG, -- 1-bit A port register set/reset inputRSTREGB => RSTREGB,-- 1-bit B port register set/reset inputWEA => WEA,-- 2-bit A port write enable inputWEBWE => WEBWE-- 4-bit B port write enable/Write enable input);-- End of RAMB18E1_inst instantiation-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"Verilog Instantiation Template// RAMB18E1: 18K-bit Configurable Synchronous Block RAM// Virtex-6// Xilinx HDL Language Template, version 11.1RAMB18E1 #(.DOA_REG(0),.DOB_REG(0),// Optional output// register on A port// (0 or 1)// Optional output// register on B port// (0 or 1)// INITP_00 to INITP_07: Allows specification of the initial contents of the 2KB parity data memory// array..INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL Designs286 www.xilinx.com UG623 (v 11.4) December 2, 2009