Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock// All FPGAs// Xilinx HDL Libraries Guide, version 11.2SRL16E #(.INIT(16’h0000) // Initial Value of Shift Register) SRL16E_inst (.Q(Q), // SRL data output.A0(A0), // Select[0] input.A1(A1), // Select[1] input.A2(A2), // Select[2] input.A3(A3), // Select[3] input.CE(CE), // Clock enable input.CLK(CLK), // Clock input.D(D) // SRL data input);// End of SRL16E_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs304 www.xilinx.com UG623 (v 11.4) December 2, 2009