Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)-- Virtex-4/5, Spartan-3/3E/3A-- Xilinx HDL Libraries Guide, version 11.2IBUFGDS_inst : IBUFGDSgeneric map (IOSTANDARD => "DEFAULT")port map (O => O, -- Clock buffer outputI => I, -- Diff_p clock buffer inputIB => IB -- Diff_n clock buffer input);-- End of IBUFGDS_inst instantiationVerilog Instantiation Template// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)// Virtex-4/5, Spartan-3/3E/3A// Xilinx HDL Libraries Guide, version 11.2IBUFGDS #(.DIFF_TERM("FALSE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A).IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer.IBUF_DELAY_VALUE("0") // Specify the amount of added input delay for// the buffer: "0"-"12" (Spartan-3E)// "0"-"16" (Spartan-3A)) IBUFGDS_inst (.O(O), // Clock buffer output.I(I), // Diff_p clock buffer input.IB(IB) // Diff_n clock buffer input);// End of IBUFGDS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 161