Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionAUTORESET_PATDETString“NO_RESET”,“RESET_MATCH”,“RESET_NOT_MATCH”“NO_RESET”Automatically reset DSP slice P Register(accumulated value or Counter Value) on thenext clock cycle if pattern detect event hasoccurred on this clock cycle.If pattern is matched, or whenever pattern is notmatched on the current cycle but was matchedon the previous clock cycle, the RESET_MATCHand RESET_NOT_MATCH settings distinguishwhether the DSP slice should cause auto reset ofP Register on the next cycle.BCASCREG Integer 1, 0, 2 1 In conjunction with BREG, selects the number ofB input registers on B cascade BCOUT. Must beequal to or one less than BREG value.B_INPUT String “DIRECT”,“CASCADE”“DIRECT”Selects between B and BCIN inputs.Selectswhether to register the A input to the DSP48.BREG Integer 1, 0, 2 1 Selects whether to register the B input to theDSP48E1.CARRYINREG Integer 1, 0 1 Set to 1 to register the CARRYIN inputs.CARRYINSELREG Integer 1, 0 1 Set to 1 to register the CARRYINSEL inputs.CREG Integer 1, 0 1 Selects whether to register the C input to theDSP48E1.DREG Integer 1, 0 1 Selects whether to register the D input to theDSP48E1.INMODEREG Integer 1, 0 1 Set to 1 to register the INMODE inputs.MASK48’h000000000000 to48’hffffffffffff48’h3fffffffffffMask to be used for pattern detector.MREG Integer 1, 0 1 Selects whether to register the multiplier stage ofthe DSP48. Enable=1/disable=0.OPMODEREG Integer 1, 0 1 Set to 1 to register the OPMODE inputs.PATTERNHexadecimalHexadecimal48’h000000000000 to48’hffffffffffffAll zerosPattern to be used for pattern detector.PREG Integer 1, 0 1 Selects whether to register the P input to theDSP48E1.SEL_MASK String “MASK”, “C”,“ROUNDING_MODE1”,“ROUNDING_MODE2”“MASK”Selects mask to be used for pattern detector. Thevalues C and MASK are for standard uses of thepattern detector (counter, overflow detection,etc.). ROUNDING_MODE1 (C-bar left shifted by1) and ROUNDING_MODE2 (C-bar left shiftedby 2) select special masks based on the optionallyregistered C port. These rounding modes can beused to implement convergent rounding in theDSP slice using the pattern detector as describedin the Virtex-6 FPGA DSP48E1 Block User Guide.SEL_PATTERN String “PATTERN”, “C” “PATTERN” Selects pattern to be used for pattern detector.USE_DPORT Boolean FALSE, TRUE FALSE Selects usage of the Pre-adder and D Port.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 125