Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsMMCM_ADVPrimitive: MMCM is a mixed signal block designed to support clock network deskew, frequencysynthesis, and jitter reduction.IntroductionThis component is a mixed signal block designed to support clock network deskew, frequency synthesis,and jitter reduction. The seven "O" counters can be independently programmed, which means O0 could beprogrammed to do a divide by 2 while O1 is programmed to do a divide by 3. The only limitation is that theVCO operating frequency must be the same for all the output counters since a single VCO drives all the counters.The CLKFBOUT and CLKFBOUTB can be used to drive logic, but it must be equal to the CLKin frequencydivided by the value of the DIVCLK_DIVIDE attribute.Port DescriptionsPort Type Width FunctionCLKFBIN Input 1 Feedback clock input.CLKFBOUT Output 1 Dedicated MMCM feedback output.CLKFBOUTB Output 1 Inverted MMCM feedback clock output.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 217