Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIBUFDSPrimitive: Differential Signaling Input BufferIntroductionThis design element is an input buffer that supports low-voltage, differential signaling. In IBUFDS, a designlevel interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the"slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P andMYNET_N). Optionally, a programmable differential termination feature is available to help improve signalintegrity and reduce external components.Logic TableInputsI IB OOutputs0 0 No Change0 1 01 0 11 1 No ChangePort DescriptionsPort Type Width FunctionI Input 1 Diff_p Buffer InputIB Input 1 Diff_n Buffer InputO Output 1 Buffer OutputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoPut all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connectthe I port directly to the top-level "master" input port of the design, the IB port to the top-level "slave" inputport, and the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.Available AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL Designs154 www.xilinx.com UG623 (v 11.4) December 2, 2009