Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort Type Width FunctionECCPARITY[7:0] Output 8 8-bit data generated by the ECC encoder used by the ECCdecoder for memory error detection and correction.EMPTY Output 1 Active high logic to indicate that the FIFO is currentlyempty.FULL Output 1 Active high logic indicates that the FIFO is full.INJECTDBITERR Input 1 Inject a double bit error if ECC feature is used.INJECTSBITERR Input 1 Inject a single bit error if ECC feature is used.RDEN Input 1 Active high FIFO read enable.REGCE Input 1 Output register clock enable for pipelined synchronousFIFO.RST Input 1 Active high (FIFO logic) asynchronous reset (for dual-clockFIFO), synchronous reset (synchronous FIFO) for 3 CLKcycles.RSTREG Input 1 Output register synchronous set/reset.SBITERR Output 1 Status output from ECC function to indicate a single biterror was detected. EN_ECC_READ needs to be TRUE inorder to use this functionality.WRCLK, RDCLK Input 1 FIFO read and write clocks (positive edge triggered).WRCOUNT,RDCOUNTOutput 13 FIFO write/read pointer.WREN Input 1 Active high FIFO write enable.WRERR,RDERROutput 1 • WRERR indicates that a write occurred while the FIFOwas full.• RDERR indicates that a read occurred while the FIFOwas empty.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionALMOST_EMPTY_OFFSETALMOST_FULL_OFFSETHexadecimalHexadecimal13’h0000 to 13’h8191 13’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_EMPTY flag.13’h0000 to 13’h8191 13’h0080 Specifies the amount of datacontents in the RAM to trigger theALMOST_FULL flag.DATA_WIDTH Integer 4, 9, 18, 36, 72 4 Specifies the desired data width forthe FIFO.DO_REG Integer 1, 0 1 Enable output register to the FIFO forimproved clock-to-out timing at theexpense of added read latency (oneVirtex-6 Libraries Guide for HDL Designs142 www.xilinx.com UG623 (v 11.4) December 2, 2009