Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsLUT6_LPrimitive: 6-Input Lookup Table with Local OutputIntroductionThis design element is a 6-input, 1-output look-up table (LUT) that can either act as an asynchronous 64-bit ROM(with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocks and areused to implement most logic functions of the design. A LUT6 is mapped to one of the four look-up tables inthe slice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_L and LUT6_Dallow the additional specification to connect the LUT6 output signal to an internal slice, or CLB connection, usingthe LO output. The LUT6_L specifies that the only connections from the LUT6 are within a slice, or CLB, whilethe LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLB logic and externallogic as well. The LUT6 does not state any specific output connections and should be used in all cases exceptwhere internal slice or CLB signal connections must be implicitly specified.An INIT attribute consisting of a 64-bit hexadecimal value must be specified to indicate the LUT’s logicalfunction. The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associatedinputs are applied. For instance, a Verilog INIT value of 64’h8000000000000000 (X"8000000000000000" forVHDL) will make the output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT valueof 64’hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) will make the output one unless all zeros are on theinputs (a 6-input OR gate).The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logictable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and is more self-documenting that the abovemethod. However, this method does require the code to first specify the appropriate parameters.Logic TableInputsI5 I4 I3 I2 I1 I0 LOOutputs0 0 0 0 0 0 INIT[0]0 0 0 0 0 1 INIT[1]Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 213