Xilinx Virtex-6 Libraries Guide for HDL Designs

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Xilinx Trademarks and Copyright InformationXilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to yousolely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,distribute, republish, download, display, post, or transmit the Documentation in any form or by any meansincluding, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the priorwritten consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinxassumes no obligation to correct any errors contained in the Documentation, or to advise you of any correctionsor updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may beprovided to you in connection with the Information.THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINXMAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDINGTHE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR APARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILLXILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THEDOCUMENTATION.© Copyright 2002-2009 Xilinx Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and otherdesignated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property oftheir respective owners.Virtex-6 Libraries Guide for HDL Designs2 www.xilinx.com UG623 (v 11.4) December 2, 2009
Table of ContentsXilinx Trademarks and Copyright Information......................................................................................... 2Chapter 1 About this Guide......................................................................................................................... 15Design Entry Methods.......................................................................................................................... 15Chapter 2 About Unimacros........................................................................................................................ 17BRAM_SDP_MACRO .......................................................................................................................... 18Introduction.................................................................................................................................. 18Port Description ............................................................................................................................ 18Configuration Table....................................................................................................................... 19Design Entry Method .................................................................................................................... 19Available Attributes ...................................................................................................................... 19For More Information.................................................................................................................... 26BRAM_SINGLE_MACRO .................................................................................................................... 27Introduction.................................................................................................................................. 27Port Description ............................................................................................................................ 27Configuration Table....................................................................................................................... 28Design Entry Method .................................................................................................................... 30Available Attributes ...................................................................................................................... 30For More Information.................................................................................................................... 35BRAM_TDP_MACRO.......................................................................................................................... 36Introduction.................................................................................................................................. 36Port Description ............................................................................................................................ 36Configuration Table....................................................................................................................... 37Design Entry Method .................................................................................................................... 39Available Attributes ...................................................................................................................... 39For More Information.................................................................................................................... 45FIFO_DUALCLOCK_MACRO ............................................................................................................. 46Introduction.................................................................................................................................. 46Port Description ............................................................................................................................ 46Configuration Table....................................................................................................................... 47Design Entry Method .................................................................................................................... 47Available Attributes ...................................................................................................................... 48For More Information.................................................................................................................... 49FIFO_SYNC_MACRO .......................................................................................................................... 50Introduction.................................................................................................................................. 50Port Description ............................................................................................................................ 50Configuration Table....................................................................................................................... 51Design Entry Method .................................................................................................................... 51Available Attributes ...................................................................................................................... 52For More Information.................................................................................................................... 53ADDMACC_MACRO .......................................................................................................................... 54Introduction.................................................................................................................................. 54Port Description ............................................................................................................................ 54Design Entry Method .................................................................................................................... 55Available Attributes ...................................................................................................................... 55For More Information.................................................................................................................... 56ADDSUB_MACRO .............................................................................................................................. 57Introduction.................................................................................................................................. 57Port Description ............................................................................................................................ 57Design Entry Method .................................................................................................................... 57Available Attributes ...................................................................................................................... 58For More Information.................................................................................................................... 59COUNTER_LOAD_MACRO ................................................................................................................ 60Introduction.................................................................................................................................. 60Port Description ............................................................................................................................ 60Design Entry Method .................................................................................................................... 60Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 3
Page 1: Virtex-6 Libraries Guide forHDL Des
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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