Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosName Direction Width FunctionRDERR Output 1 When the FIFO is empty, any additional read operationgenerates an error flag.WRCOUNT Output SeeConfigurationTable below.FIFO data write pointer.WRERR Output 1 When the FIFO is full, any additional write operationgenerates an error flag.Input PortsDI Input SeeConfigurationTable below.Data input bus addressed by ADDR.RDCLK Input 1 Clock for Read domain operation.RDEN Input 1 Read EnableRST Input 1 Asynchronous reset.WRCLK Input 1 Clock for Write domain operation.WREN Input 1 Write EnableConfiguration TableThis unimacro can be instantiated only. The unimacro is a parameterizable version of the primitive. Please usethe Configuration Table below to correctly configure the unimacro to meet design needs.DATA_WIDTH FIFO_SIZE WRCOUNT RDCOUNT72 - 37 36kb 9 936 - 1918 - 109-51-436kb 10 1018kb 9 936kb 11 1118kb 10 1036kb 12 1218kb 11 1136kb 13 1318kb 12 12Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the aboveConfiguration Table to correctly configure this element to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 47