Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About Unimacros-- width determined by WIDTH_PRODUCT genericRST => RST -- 1-bit input active high reset);-- End of ADDMACC_MACRO_inst instantiationVerilog Instantiation Template// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate// function implemented in a DSP48E// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2ADDMACC_MACRO #(.DEVICE("VIRTEX5"), // Target Device: "VIRTEX6", "SPARTAN6".LATENCY(2), // Desired clock cycle latency, 0-2.WIDTH_PREADD(25), // Pre-adder inputwidth, 1-25.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18.WIDTH_PRODUCT(48) // MACC output width, 1-48) ADDMACC_MACRO_inst (.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter.CARRYIN(CARRYIN), // 1-bit carry-in input.CLK(CLK),// 1-bit clock input.CE(CE),// 1-bit clock enable input.LOAD(LOAD),// 1-bit accumulator load input.LOAD_DATA(LOAD_DATA), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter.PREADD2(PREADD2), // Preadder data input, width defined by WIDTH_PREADD parameter.PREADD1(PREADD1), // Preadder data input, width defined by WIDTH_PREADD parameter.RST(RST)// 1-bit active high synchrnous reset);// End of ADDMACC_MACRO_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs56 www.xilinx.com UG623 (v 11.4) December 2, 2009