Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// LUT5: 5-input Look-Up Table with general output// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2LUT5 #(.INIT(32’h00000000) // Specify LUT Contents) LUT5_inst (.O(O), // LUT general output.I0(I0), // LUT input.I1(I1), // LUT input.I2(I2), // LUT input.I3(I3), // LUT input.I4(I4) // LUT input);// End of LUT5_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs196 www.xilinx.com UG623 (v 11.4) December 2, 2009