Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsLDPEPrimitive: Transparent Data Latch with Asynchronous Preset and Gate EnableIntroductionThis design element is a transparent data latch with asynchronous preset and gate enable. When theasynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflectsthe data (D) input while the gate (G) input and gate enable (GE) are High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) or (GE) remains Low.The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.Logic TableInputsOutputsPRE GE G D Q1 X X X 10 0 X X No Change0 1 1 D D0 1 0 X No Change0 1 ↓ D DDesign Entry MethodThis design element is only for use in schematics.Available AttributesAttribute Type Allowed Values Default DescriptionINIT Binary 0, 1 1 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs188 www.xilinx.com UG623 (v 11.4) December 2, 2009