Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosName Direction Width FunctionRST Input 1 Synchronous Reset.ADDSUB Input 1 High sets accumulator in addition mode; low setsaccumulator in subtraction mode.Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.InstantiationInferenceCORE Generator and wizardsMacro supportAvailable AttributesYesNoNoRecommendedAttribute Type Allowed Values Default DescriptionWIDTH_A Integer 1 to 25 25 Controls the width of A input.WIDTH_B Integer 1 to 18 18 Controls the width of B inputLATENCY Integer 0, 1, 2, 3, 4 3 Number of pipeline registersDEVICE String “VIRTEX6”,“SPARTAN6”VHDL Instantiation Template“VIRTEX6”• 1 - MREG == 1• 2 - AREG == BREG == 1 and MREG== 1 or MREG == 1 and PREG == 1• 3 - AREG == BREG == 1 and MREG== 1 and PREG == 1• 4 - AREG == BREG == 2 and MREG== 1 and PREG == 1Target hardware architecture.Unless they already exist, copy the following two statements and paste them before the entity declaration.library UNIMACRO;use unimacro.Vcomponents.all;-- MACC_MACRO: Multiple Accumulate Function implemented in a DSP48E-- Virtex-5, Virtex-6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2MACC_MACRO_inst : MACC_MACROgeneric map (DEVICE => "VIRTEX5", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"LATENCY => 3, -- Desired clock cycle latency, 1-4WIDTH_A => 25, -- Multiplier A-input bus width, 1-25WIDTH_B => 18, -- Multiplier B-input bus width, 1-18WIDTH_P => 48) -- Accumulator output bus width, 1-48port map (P => P, -- MACC ouput bus, width determined by WIDTH_P genericA => A, -- MACC input A bus, width determined by WIDTH_A genericADDSUB => ADDSUB, -- 1-bit add/sub input, high selects add, low selects subtractB => B,-- MACC input B bus, width determined by WIDTH_B genericCARRYIN => CARRYIN, -- 1-bit carry-in input to accumulatorCE => CE, -- 1-bit active high input clock enableCLK => CLK, -- 1-bit positive edge clock inputVirtex-6 Libraries Guide for HDL Designs70 www.xilinx.com UG623 (v 11.4) December 2, 2009