Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 2: About UnimacrosEQ_COMPARE_MACROMacro: Equality ComparatorIntroductionThe EQ_COMPARE_MACRO simplifies the instantiation of the DSP48 block when used as an equalitycomparator. It features parameterizable input and output widths, latencies, mask, and input sources thatease the integration of the DSP48 block into HDL.Port DescriptionName Direction Width FunctionOutput PortsQ Output 1 Active High pattern detection. Detectsmatch of DATA_IN and the selectedDYNAMIC_PATTERN gated by the MASK.Result arrives on the same cycle as P.Input PortsDATA_IN Input Variable width, equals the valueof the WIDTH attribute.DYNAMIC_PATTERN Input Variable width, equals the valueof the WIDTH attribute.CLK Input 1 ClockCE Inupt 1 Clock enableInput data to be comparedRST Input 1 Synchronous ResetDynamic data to be compared to DATA_INDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive.Virtex-6 Libraries Guide for HDL Designs66 www.xilinx.com UG623 (v 11.4) December 2, 2009