Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionSIM_DNA_VALUEHexadecimal57’h000000000000000 to57’h1ffffffffffffff57’h000000000000000Specifies a DNA value for simulationpurposes (the actual value is particular tothe specific device used).For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs120 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design ElementsDSP48E1Primitive: 25x18 Two’s Complement Multiplier with Integrated 48-Bit, 3-InputAdder/Subtracter/Accumulator or 2-Input Logic UnitIntroductionThis design element is a versatile, scalable, hard IP block within Virtex®-6 that allows for the creation of compact,high-speed, arithmetic-intensive operations, such as those seen for many DSP algorithms. Some of the functionscapable within the block include multiplication, addition (including pre-adder), subtraction, accumulation,shifting, logical operations, and pattern detection.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 121
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Virtex-6 Libraries Guide forHDL Des
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Table of ContentsXilinx Trademarks
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Available Attributes ..............
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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