Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort DescriptionsPort Direction Width FunctionQ Output 1 Shift register data outputD Input 1 Shift register data inputCLK Input 1 ClockCE Input 1 Active high clock enableA Input 4 Dynamic depth selection of the SRL• A=0000 ==> 1-bit shift length• A=1111 ==> 16-bit shift lengthDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionINITHexadecimalAny 16-Bit Value All zeros Sets the initial value of content and output of shiftregister after configuration.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock-- All FPGAs-- Xilinx HDL Libraries Guide, version 11.2SRL16E_inst : SRL16Egeneric map (INIT => X"0000")port map (Q => Q, -- SRL data outputA0 => A0, -- Select[0] inputA1 => A1, -- Select[1] inputA2 => A2, -- Select[2] inputA3 => A3, -- Select[3] inputCE => CE, -- Clock enable inputCLK => CLK, -- Clock inputD => D -- SRL data input);-- End of SRL16E_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 303