Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsCLKOUT1_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT2_DIVIDE => 1, -- Counter divide valueCLKOUT2_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT2_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT3_DIVIDE => 1, -- Counter divide valueCLKOUT3_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT3_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT4_CASCADE => FALSE,CLKOUT4_DIVIDE => 1, -- Counter divide valueCLKOUT4_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT4_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT5_DIVIDE => 1, -- Counter divide valueCLKOUT5_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT5_PHASE => 0.0, -- Counter output phase relative to the output clockCLKOUT6_DIVIDE => 1, -- Counter divide valueCLKOUT6_DUTY_CYCLE => 0.5, -- Counter output duty cycleCLKOUT6_PHASE => 0.0, -- Counter output phase relative to the output clockCLOCK_HOLD => FALSE,DIVCLK_DIVIDE => 1,-- Counter divide value, always configured for 50% duty cycleREF_JITTER1 => 0.0,-- The reference clock2 jitter is specified in terms of the UI which is a-- percentage of the reference clock. The number provided should be the-- maximum peak to peak value our part can expect on the input clock. Default-- is 0.1UI. This parameter should support out to three decimal places.STARTUP_WAIT => FALSE -- When TRUE, the MMCM locks before DONE goes high)port map (CLKFBOUT => CLKFBOUT, -- 1-bit MMCM Feedback clock outputCLKFBOUTB => CLKFBOUTB, -- 1-bit Inverted MMCM feedback clock outputCLKOUT0 => CLKOUT0, -- 1-bit MMCM clock output 0CLKOUT0B => CLKOUT0B, -- 1-bit Inverted MMCM clock output 0CLKOUT1 => CLKOUT1, -- 1-bit MMCM clock output 1CLKOUT1B => CLKOUT1B, -- 1-bit Inverted MMCM clock output 1CLKOUT2 => CLKOUT2, -- 1-bit MMCM clock output 2CLKOUT2B => CLKOUT2B, -- 1-bit Inverted MMCM clock output 2CLKOUT3 => CLKOUT3, -- 1-bit MMCM clock output 3CLKOUT3B => CLKOUT3B, -- 1-bit Inverted MMCM clock output 3CLKOUT4 => CLKOUT4, -- 1-bit MMCM clock output 4CLKOUT5 => CLKOUT5, -- 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integerCLKOUT6 => CLKOUT6, -- 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integerLOCKED => LOCKED, -- 1-bit MMC locked signalCLKFBIN => CLKFBIN, -- 1-bit Feedback clock pin to the MMCMCLKIN1 => CLKIN1, -- 1-bit Reference clock pin 1 to the MMCMPWRDWN => PWRDWN, -- 1-bit Power downRST => RST-- 1-bit MMCM global reset pin);-- End of MMCM_BASE_inst instantiationVerilog Instantiation Template// MMCM_BASE: MMCM is a mixed signal block designed to support clock network deskew, frequency synthesis, and jitter reduction.// Virtex-6// Xilinx HDL Language Template, version 11.1MMCM_BASE #(.BANDWIDTH("OPTIMIZED"), // PLL bandwidth control, sets the MMCM bandwidth. Selecting HIGH sets the// MMCM programming algorithm to the highest setting possible while// maintaining good MMCM performance (i.e. low jitter, low jitter peaking,// maximum phase margin). Selecting LOW sets the MMCM algorithm to the lowest// setting possible while maintaining good MMCM performance. Selecting// Optimized allows the MMCM programming algorithm to configure the MMCM in// the best performance mode without trying to reach any particular bandwidth..CLKFBOUT_MULT_F(1.0), // Counter multiply value, Now supports non-integer values.CLKFBOUT_PHASE(0.0), // Only supported when CLKFBOUT_MULT is an integer value.CLKIN1_PERIOD(0.0), // The reference clock frequency is required for properly configuring the LOCK// detect circuit and checking to make sure the VCO is operating within the// allowed range. If no value is specified, a warning should be issued stating// it was not provided so no error checking will be done..CLKOUT0_DIVIDE_F(1.0), // Counter divide value, Now supports non-integer values but you lose CLKOUT5.CLKOUT0_DUTY_CYCLE(0.5),.CLKOUT0_PHASE(0.0),// Counter output duty cycle// Counter output phase relative to the output clock, only supported when// CLKOUT0_DIVIDE is an integer value.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 227