Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsRAM128X1DPrimitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)IntroductionThis design element is a 128-bit deep by 1-bit wide random access memory and has a read/write port that writesthe value on the D input data pin when the write enable (WE) is high to the location specified by the A addressbus. This happens shortly after the rising edge of the WCLK and that same value is reflected in the data outputSPO. When WE is low, an asynchronous read is initiated in which the contents of the memory location specifiedby the A address bus is output asynchronously to the SPO output. The read port can perform asynchronousread access of the memory by changing the value of the address bus DPRA, and by outputing that value to theDPO data output.Port DescriptionsPort Direction Width FunctionSPO Output 1 Read/Write port data output addressed by ADPO Output 1 Read port data output addressed by DPRAD Input 1 Write data input addressed by AA Input 7 Read/Write port address busDPRA Input 7 Read port address busWE Input 1 Write EnableWCLK Input 1 Write clock (reads are asynchronous)If instantiated, the following connections should be made to this component:• Tie the WCLK input to the desired clock source, the D input to the data source to be stored and the DPOoutput to an FDCE D input or other appropriate data destination.• Optionally, the SPO output can also be connected to the appropriate data destination or else left unconnected.• The WE clock enable pin should be connected to the proper write enable source in the design.• The 7-bit A bus should be connected to the source for the read/write addressing and the 7-bit DPRA busshould be connected to the appropriate read address connections.• An optional INIT attribute consisting of a 128-bit Hexadecimal value can be specified to indicate the initialcontents of the RAM.If left unspecified, the initial contents default to all zeros.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 261