Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 2: About UnimacrosBRAM_SDP_MACROMacro: Simple Dual Port RAMIntroductionFPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kbRAM/ROM memories. These block RAM memories offer fast and flexible storage of large amounts of on-chipdata. Both read and write operations are fully synchronous to the supplied clock(s) of the component. However,READ and WRITE ports can operate fully independently and asynchronously to each other, accessing thesame memory array. Byte-enable write operations are possible, and an optional output register can be used toreduce the clock-to-out times of the RAM.Note This element, must be configured so that read and write ports have the same width.Port DescriptionName Direction Width (Bits) FunctionOutput PortsDO Output See Configuration Table Data output bus addressed by RDADDR.Input PortsDI Input See Configuration Table Data input bus addressed by WRADDR.WRADDR,RDADDRInput See Configuration Table Write/Read address input buses.WE Input See Configuration Table Byte-Wide Write enable.Virtex-6 Libraries Guide for HDL Designs18 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 2: About UnimacrosName Direction Width (Bits) FunctionWREN,RDENInput 1 Write/Read enableSSR Input 1 Output registers synchronous reset.REGCE Input 1 Output register clock enable input (valid onlywhen DO_REG=1)WRCLK,RDCLKInput 1 Write/Read clock input.Configuration TableDATA_WIDTH BRAM_SIZE ADDR WE72 - 37 36kb 9 836 - 1936kb 10418kb 918 - 1036kb 11218kb 109 - 536kb 12118kb 114 - 336kb 13118kb 12236kb 14118kb 13136kb 15118kb 14Design Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the ConfigurationTable above to correctly configure it to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute Type Allowed Values Default DescriptionBRAM_SIZE String “18kb”, “36kb” “18kb” Configures RAM as 18kb or 36kbmemory.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 19
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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