Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- MUXF8_D: CLB MUX to tie two MUXF7’s together with general and local outputs-- For use with all FPGAs-- Xilinx HDL Libraries Guide, version 11.2MUXF8_D_inst : MUXF8_Dport map (LO => LO, -- Ouptut of MUX to local routingO => O, -- Output of MUX to general routingI0 => I0, -- Input (tie to MUXF7 LO out)I1 => I1, -- Input (tie to MUXF7 LO out)S => S -- Input select to MUX);-- End of MUXF8_D_inst instantiationVerilog Instantiation Template// MUXF8_D: CLB MUX to tie two MUXF7’s together with general and local outputs// For use with all FPGAs// Xilinx HDL Libraries Guide, version 11.2MUXF8_D MUXF8_D_inst (.LO(LO), // Ouptut of MUX to local routing.O(O), // Output of MUX to general routing.I0(I0), // Input (tie to MUXF7 LO out).I1(I1), // Input (tie to MUXF7 LO out).S(S) // Input select to MUX);// End of MUXF8_D_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs238 www.xilinx.com UG623 (v 11.4) December 2, 2009