Xilinx Virtex-6 Libraries Guide for HDL Designs
Xilinx Virtex-6 Libraries Guide for HDL Designs
Xilinx Virtex-6 Libraries Guide for HDL Designs
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Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionDRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Selects output drive strength (mA)<strong>for</strong> the SelectIO buffers that usethe LVTTL, LVCMOS12, LVCMOS15,LVCMOS18, LVCMOS25, or LVCMOS33interface I/O standard.IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.SLEW String "SLOW", "FAST","QUIETIO""SLOW"Sets the output rise and fall time. See theData Sheet <strong>for</strong> recommendations of thebest setting <strong>for</strong> this attribute.V<strong>HDL</strong> Instantiation TemplateUnless they already exist, copy the following two statements and paste them be<strong>for</strong>e the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IOBUF: Single-ended Bi-directional Buffer-- All devices-- <strong>Xilinx</strong> <strong>HDL</strong> <strong>Libraries</strong> <strong>Guide</strong>, version 11.2IOBUF_inst : IOBUFgeneric map (DRIVE => 12,IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay <strong>for</strong> buffer,-- "0"-"12" (Spartan-3E)-- "0"-"16" (Spartan-3A)IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay <strong>for</strong> input register,-- "AUTO", "0"-"6" (Spartan-3E)-- "AUTO", "0"-"8" (Spartan-3A)IOSTANDARD => "DEFAULT",SLEW => "SLOW")port map (O => O, -- Buffer outputIO => IO, -- Buffer inout port (connect directly to top-level port)I => I, -- Buffer inputT => T -- 3-state enable input, high=input, low=output);-- End of IOBUF_inst instantiationVerilog Instantiation Template// IOBUF: Single-ended Bi-directional Buffer// All devices// <strong>Xilinx</strong> <strong>HDL</strong> <strong>Libraries</strong> <strong>Guide</strong>, version 11.2IOBUF #(.DRIVE(12), // Specify the output drive strength.IBUF_DELAY_VALUE("0"),// Specify the amount of added input delay <strong>for</strong> the buffer,// "0"-"12" (Spartan-3E only), "0"-"16" (Spartan-3A only).IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay <strong>for</strong> input register,// "AUTO", "0"-"6" (Spartan-3E only), "0"-"8" (Spartan-3A only).IOSTANDARD("DEFAULT"), // Specify the I/O standard.SLEW("SLOW") // Specify the output slew rate) IOBUF_inst (.O(O),.IO(IO),.I(I),.T(T));// Buffer output// Buffer inout port (connect directly to top-level port)// Buffer input// 3-state enable input, high=input, low=output// End of IOBUF_inst instantiation<strong>Virtex</strong>-6 <strong>Libraries</strong> <strong>Guide</strong> <strong>for</strong> <strong>HDL</strong> <strong>Designs</strong>UG623 (v 11.4) December 2, 2009 www.xilinx.com 171
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