Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// BUFIODQS: Differential Clock Input for Transceiver Reference Clocks// Virtex-6// Xilinx HDL Language Template, version 11.1BUFIODQS #(.DQSMASK_ENABLE("FALSE") // Enables the squelch circuitry)BUFIODQS_inst (.O(O),// 1-bit Clock output port.DQSMASK(DQSMASK), // 1-bit "squelch" the I/O clock after a given burst length from strobe.I(I)// 1-bit Clock input port);// End of BUFIODQS_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 107