Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBUFGCTRLPrimitive: Global Clock MUX BufferIntroductionBUFGCTRL primitive is global clock buffer that is designed as a synchronous/asynchronous "glitch free" 2:1multiplexer with two clock inputs. Unlike global clock buffers that are found in previous generation of FPGAs,these clock buffers are designed with more control pins to provide a wider range of functionality and morerobust input switching. BUFGCTRL is not limited to clocking applications.Port DescriptionsPort Type Width FunctionO Output 1 Clock Output pinI Input 1 Clock Input:I0 - Clock Input PinI1 - Clock Input PinCE0, CE1 Input 1 (each) Clock Enable Input. The CE pins represent the clock enable pinfor each clock inputs and are used to select the clock inputs. Asetup/hold time must be specified when you are using the CE pinto select inputs. Failure to meet this requirement could result ina clock glitch.S0, S1 Input 1 (each) Clock Select Input. The S pins represent the clock select pin foreach clock inputs. When using the S pin as input select, there is asetup/hold time requirement. Unlike CE pins, failure to meet thisrequirement won’t result in a clock glitch. However, it can cause theoutput clock to appear one clock cycle later.IGNORE0, IGNORE1 Input 1 (each) Clock Ignore Input. IGNORE pins are used whenever a designerwants to bypass the switching algorithm executed by the BUFGCTRL.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL Designs92 www.xilinx.com UG623 (v 11.4) December 2, 2009