Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort DescriptionsPort Type Width FunctionA[29:0] Input 30 25-bit data input to Multiplier, Pre-adder, or 30-bit MSB Data Inputto Adder/Logic Unit.ACIN[29:0] Input 30 Cascade input for Port A. If used, connect to ACOUT of upstreamcascaded DSP slice. If not used, tie port to all zeros.ACOUT[29:0] Output 30 Cascade output for Port A. If used, connect to ACIN of downstreamcascaded DSP slice. If not used, leave unconnected.ALUMODE[3:0] Input 4 Control input to select Logic Unit functions including addition andsubtraction.B[17:0] Input 18 18-bit data input to Multiplier, or 18-bit LSB Data Input toAdder/Logic Unit.BCIN[17:0] Input 18 Cascade input for Port B. If used, connect to BCOUT of upstreamcascaded DSP slice. If not used, tie port to all zeros.BCOUT[17:0] Output 18 Cascade output for Port B. If used, connect to BCIN of downstreamcascaded DSP slice. If not used, leave unconnected.C[47:0] Input 48 48-bit data input to Adder/Logic Unit and Pattern Detector.CARRYCASCIN Input 1 Cascaded CARRYOUT from upstream DSP slice.CARRYCASCOUT Output 1 Cascaded CARRYOUT to downstream DSP slice.CARRYIN Input 1 External carry input to the Adder/Logic Unit.CARRYINSEL[2:0] Input 3 Selects carry-in source to the DSP slice.CARRYOUT[3:0] Output 4 Carry out signal for arithmetic operations (addition, subtraction,etc.).• If USE_SIMD="FOUR12", CARRYOUT represents the carry-outof each 12 bit field of the Accumulate/Adder/Logic Unit.• If USE_SIMD="TWO24" CARRYOUT and CARRYOUT representthe carry-out of each 24-bit field of the Accumulator/Adder.• If USE_SIMD="ONE48", CARRYOUT is the only valid carry outfrom the Accumulate/Adder/Logic Unit.CEAD Input 1 Active High, clock enable for pre-adder output AD pipeline register.Tie to logic one if not used and ADREG=1. Tie to logic zero ifADREG=0.CEALUMODE Input 1 Active High, clock enable for the ALUMODE input registers(ALUMODEREG=1). Tie to logic one if not used.CEA1 Input 1 Active High, clock enable for the A port registers (AREG=2). Tieto logic one if not used and AREG=2. Tie to logic zero if AREG=0or 1. When two registers are used, this is the first sequentially.When Dynamic AB Access is used, this clock enable is applied forINMODE=1.CEA2 Input 1 Active High, clock enable for the A port registers. Tie to logic one ifnot used and AREG=1 or 2. Tie to logic zero if AREG=0. When tworegisters are used, this is the second sequentially. When one registeris used (AREG=1), CEA2 is the clock enable.CEB1 Input 1 Active High, clock enable for the B port registers (BREG=2). Tieto logic one if not used and BREG=2. Tie to logic zero if BREG=0or 1. When two registers are used, this is the first sequentially.When Dynamic AB Access is used, this clock enable is applied forINMODE=1.Virtex-6 Libraries Guide for HDL Designs122 www.xilinx.com UG623 (v 11.4) December 2, 2009