Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// USR_ACCESS_VIRTEX6: Virtex-6 User Access Register// Virtex-6// Xilinx HDL Language Template, version 11.1USR_ACCESS_VIRTEX6 USR_ACCESS_VIRTEX6_inst (.CFGCLK(CFGCLK), // 1-bit Configuration Clock.DATA(DATA),// 32-bit Configuration Output Data.DATAVALID(DATAVALID) // 1-bit Active high DATA port contains valid data);// End of USR_ACCESS_VIRTEX6_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs320 www.xilinx.com UG623 (v 11.4) December 2, 2009