Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsOBUFPrimitive: Output BufferIntroductionThis design element is a simple output buffer used to drive output signals to the FPGA device pins that do notneed to be 3-stated (constantly driven). Either an OBUF, OBUFT, OBUFDS, or OBUFTDS must be connected toevery output port in the design.This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.Port DescriptionsPort Direction Width FunctionO Output 1 Output of OBUF to be connected directly to top-level outputport.I Input 1 Input of OBUF. Connect to the logic driving the output port.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 241