Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIDDRPrimitive: Input Dual Data-Rate RegisterIntroductionThis design element is a dedicated input register designed to receive external dual data rate (DDR) signals intoXilinx® FPGAs.The IDDR is available with modes that present the data to the FPGA fabric at the time andclock edge they are captured, or on the same clock edge. This feature allows you to avoid additional timingcomplexities and resource usage.• OPPOSITE_EDGE mode - Data is recovered in the classic DDR methodology. Given a DDR data andclock at pin D and C respectively, Q1 changes after every positive edge of clock C, and Q2 changes afterevery negative edge of clock C.• SAME_EDGE mode - Data is still recovered by opposite edges of clock C. However, an extra register has beenplaced in front of the negative edge data register. This extra register is clocked with positive clock edge ofclock signal C. As a result, DDR data is now presented into the FPGA fabric at the same clock edge. However,because of this feature, the data pair appears to be "separated." Q1 and Q2 no longer have pair 1 and 2.Instead, the first pair presented is Pair 1 and DONT_CARE, followed by Pair 2 and 3 at the next clock cycle.• SAME_EDGE_PIPELINED mode - Recovers data in a similar fashion as the SAME_EDGE mode. In orderto avoid the "separated" effect of the SAME_EDGE mode, an extra register has been placed in front of thepositive edge data register. A data pair now appears at the Q1 and Q2 pin at the same time. However, usingthis mode costs you an additional cycle of latency for Q1 and Q2 signals to change.IDDR also works with the SelectIO features, such as the IODELAY.Note For high speed interfaces, the IDDR_2CLK component can be used to specify two independent clocksto capture the data. Use this component when the performance requirements of the IDDR are not adequate,since the IDDR_2CLK requires more clocking resources and can imply placement restrictions that are notnecessary when using the IDDR component.Port DescriptionsPort Direction Width FunctionQ1 - Q2 Output 1 These pins are the IDDR output that connects to the FPGA fabric. Q1 isthe first data pair and Q2 is the second data pair.C Input 1 Clock input pin.CE Input 1 When asserted Low, this port disables the output clock at port O.D Input 1 This pin is where the DDR data is presented into the IDDR module.This pin connects to a top-level input or bi-directional port, andIODELAY configured for an input delay or to an appropriate input orbidirectional buffer.R Input 1 Active high reset forcing Q1 and Q2 to a logic zero. Can be synchronousor asynchronous based on the SRTYPE attribute.S Input 1 Active high reset forcing Q1 and Q2 to a logic one. Can be synchronousor asynchronous based on the SRTYPE attribute.Virtex-6 Libraries Guide for HDL Designs164 www.xilinx.com UG623 (v 11.4) December 2, 2009