Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBUFHConvenience Primitive: Clock buffer for a single clocking regionIntroductionThe BUFH primitive is provided to allow instantiation capability to access the HCLK clock buffer resources.Port DescriptionsPort Type Width FunctionI Input 1 Clock InputO Output 1 Clock OutputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoNoVHDL Instantiation Template-- BUFH: (Clock buffer for a single clocking region)-- Spartan-6-- Xilinx HDL Libraries Guide, version 11.4BUFH_inst : BUFHgeneric map ()port map (O => O, -- 1-bit Clock OutputI => I -- 1-bit Clock Input);-- End of BUFH_inst instantiationVerilog Instantiation Template// BUFH: Clock buffer for a single clocking region// Virtex-6// Xilinx HDL Language Template, version 11.4BUFH BUFH_inst (.O(O), // 1-bit The output to the BUFH.I(I) // 1-bit The input to the BUFH);// End of BUFH_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 101