Xilinx Virtex-6 Libraries Guide for HDL Designs
Xilinx Virtex-6 Libraries Guide for HDL Designs
Xilinx Virtex-6 Libraries Guide for HDL Designs
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Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionINIT_Q1 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q1 output.INIT_Q2 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q2 output.INIT_Q3 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q3 output.INIT_Q4 Binary 1’b0 to 1’b1 1’b0 Defines the initial value of Q4 output.INTERFACE_TYPE String “MEMORY”,“MEMORY_DDR3”,“MEMORY_QDR”,“NETWORKING”IOBDELAY String “NONE”,“BOTH”,“IBUF”,“IFD”“MEMORY”“NONE”Memory or Networking interface type.Allows the user to either have adelayed or non-delayed version of theinput to the registered (Q1 - Q6) orcombinatorial path (O) output.NUM_CE Integer 2, 1 2 Specifies the number of clock enablesused <strong>for</strong> the ISERDES_NODELAY.OFB_USED Boolean FALSE, TRUE FALSE Will select the sneak path from theOLOGIC, OSERDES.SERDES_MODE String “MASTER”,“SLAVE”“MASTER”Specify whether the ISERDES isoperating in master or slave modeswhen cascaded width expansion.SRVAL_Q1 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q1 output whenthe SR is invoked.SRVAL_Q2 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q2 output whenthe SR is invoked.SRVAL_Q3 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q3 output whenthe SR is invoked.SRVAL_Q4 Binary 1’b0 to 1’b1 1’b0 Defines the value of Q4 output whenthe SR is invoked.V<strong>HDL</strong> Instantiation Template-- ISERDESE1: (Input SERial/DESerializer)-- <strong>Virtex</strong>-6-- <strong>Xilinx</strong> <strong>HDL</strong> <strong>Libraries</strong> <strong>Guide</strong>, version 11.2ISERDESE1_inst : ISERDESE1generic map (DATA_RATE => "DDR",DATA_WIDTH => 4,DYN_CLKDIV_INV_EN => FALSE,DYN_CLK_INV_EN => FALSE,INIT_Q1 => "0",INIT_Q2 => "0",INIT_Q3 => "0",INIT_Q4 => "0",INTERFACE_TYPE => "MEMORY",IOBDELAY => "NONE",NUM_CE => 2,OFB_USED => FALSE,SERDES_MODE => "MASTER",-- Single Data Rate or Double Data Rate operation.-- Parallel data width selection.-- Enables dynamic CLKDIV inversion <strong>for</strong> Memory interfaces when TRUE.-- Enables dynamic CLK inversion <strong>for</strong> Memory interfaces when TRUE.-- Defines the initial value of Q1 output.-- Defines the initial value of Q2 output.-- Defines the initial value of Q3 output.-- Defines the initial value of Q4 output.-- Memory or Networking interface type.-- Specifies the number of clock enables used <strong>for</strong> the ISERDES_NODELAY.-- Will select the sneak path from the OLOGIC, OSERDES.-- Specify whether the ISERDES is operating in master or slave modes when-- cascaded width expansion.SRVAL_Q1 => "0",-- Defines the value of Q1 output when the SR is invoked.SRVAL_Q2 => "0",-- Defines the value of Q2 output when the SR is invoked.SRVAL_Q3 => "0",-- Defines the value of Q3 output when the SR is invoked.SRVAL_Q4 => "0"-- Defines the value of Q4 output when the SR is invoked.)port map (O => O,-- 1-bit Combinatorial output.-- Q1 - Q6: 1-bit (each) Registered parallelized input data.<strong>Virtex</strong>-6 <strong>Libraries</strong> <strong>Guide</strong> <strong>for</strong> <strong>HDL</strong> <strong>Designs</strong>UG623 (v 11.4) December 2, 2009 www.xilinx.com 181
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