Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsPort Type Width FunctionRSTALLCARRYIN Input 1 Active High, synchronous reset for all carry-in registers(CARRYINREG=1). Tie to logic zero if not used.RSTALUMODE Input 1 Active High, synchronous reset for the ALUMODE registers(ALUMODEREG=1). Tie to logic zero if not used.RSTB Input 1 Active High, synchronous reset for the B port registers (BREG=1 or2). Tie to logic zero if not used.RSTC Input 1 Active High, synchronous reset for the C port registers (CREG=1).Tie to logic zero if not used.RSTCTRL Input 1 Active High, synchronous reset for the OPMODE and CARRYINSELregisters (OPMODEREG=1 and CARRYINSELREG=1). Tie to logiczero if not used.RSTD Input 1 Active High, synchronous reset for the D port registers (DREG=1).Tie to logic zero if not used.RSTINMODE Input 1 Active High, synchronous reset for the INMODE registers(INMODEREG=1). Tie to logic zero if not used.RSTM Input 1 Active High, synchronous reset for the multiplier registers(MREG=1). Tie to logic zero if not used.RSTP Input 1 Active High, synchronous reset for the output registers (PREG=1).Tie to logic zero if not used.UNDERFLOW Output 1 Active High output detects underflow in addition/accumulate ifpattern detector is used and PREG = 1.Design Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedYesYesAvailable AttributesAttribute Type Allowed Values Default DescriptionACASCREG Integer 1, 0, 2 1 In conjunction with AREG, selects the number ofA input registers on A cascade ACOUT. Must beequal to or one less than AREG value.ADREG Integer 1, 0 1 Selects usage of Pre-adder output (AD) PipelineRegisters. Set to 1 to use the AD PipelineRegisters.A_INPUT String “DIRECT”,“CASCADE”“DIRECT”Selects between A and ACIN inputs.ALUMODEREG Integer 1, 0 1 Set to 1 to register the ALUMODE inputs.AREG Integer 1, 0, 2 1 Selects whether to register the A input to theDSP48E1.Virtex-6 Libraries Guide for HDL Designs124 www.xilinx.com UG623 (v 11.4) December 2, 2009