Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBUFGMUXConvenience Primitive: Global Clock MUX BufferIntroductionBUFGMUX is a multiplexed global clock buffer that can select between two input clocks: I0 and I1. When theselect input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal onI1 is selected for output.BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when that output switchesbetween clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1assumes output state 1.Note BUFGMUX guarantees that when S is toggled, the state of the output remains in the inactive state until thenext active clock edge (either I0 or I1) occurs.Logic TableInputsOutputsI0 I1 S OI0 X 0 I0X I1 1 I1X X ↑ 0X X ↓ 0Port DescriptionsPort Type Width FunctionI0 Input 1 Clock0 inputI1 Input 1 Clock1 inputO Output 1 Clock MUX outputS Input 1 Clock select inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoVirtex-6 Libraries Guide for HDL Designs94 www.xilinx.com UG623 (v 11.4) December 2, 2009