Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 2: About UnimacrosConfiguration TableWRITE_WIDTH READ_WIDTH BRAM_SIZE ADDR WE36 - 1936 - 19 36kb10418-10 119 - 5 124 - 3 132 1411518 - 1036 - 19 36kb11218-10 119 - 5 124 - 3 132 141159 - 536-19 36kb12118-10 129 - 5 124 - 3 132 141154 - 336-19 36kb13118-10 139 - 5 134 - 3 132 14115236-19 36kb14118-10 149 - 5 144 - 3 142 14115Virtex-6 Libraries Guide for HDL Designs28 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 2: About UnimacrosWRITE_WIDTH READ_WIDTH BRAM_SIZE ADDR WE136 - 19 36kb15118 - 10 159 - 5 153 - 4 152 1511518-109 - 54 - 32118-10 18kb109 - 5 114 - 3 122 1311418-10 18kb119 - 5 114 - 3 122 1311418-10 18kb129 - 5 124 - 3 122 1311418-10 18kb139 - 5 134 - 3 132 1311418-10 18kb149 - 5 144 - 3 142 1411421111Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 29
Page 1 and 2: Virtex-6 Libraries Guide forHDL Des
Page 3 and 4: Table of ContentsXilinx Trademarks
Page 5 and 6: Available Attributes ..............
Page 7 and 8: Port Descriptions..................
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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