Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVHDL Instantiation Template-- ICAP_VIRTEX6: Internal Configuration Access Port-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2ICAP_VIRTEX6_inst : ICAP_VIRTEX6generic map (ICAP_AUTO_SWITCH => "DISABLE",ICAP_WIDTH => "X8")port map (BUSY => BUSY,O => O,CLK => CLK,CSB => CSB,I => I,RDWRB => RDWRB);-- Specifies the input and output data width to be used with the-- ICAP_VIRTEX6.-- 1-bit Busy/Ready output-- 32-bit Configuration data output bus-- 1-bit Clock Input-- 1-bit Active-Low ICAP Enable-- 32-bit Configuration data input bus-- 1-bit Read/Write Select-- End of ICAP_VIRTEX6_inst instantiationVerilog Instantiation Template// ICAP_VIRTEX6: Internal Configuration Access Port// Virtex-6// Xilinx HDL Language Template, version 11.1ICAP_VIRTEX6 #(.ICAP_AUTO_SWITCH("DISABLE"),.ICAP_WIDTH("X8"))ICAP_VIRTEX6_inst (.BUSY(BUSY), // 1-bit Busy/Ready output.O(O),// 32-bit Configuration data output bus.CLK(CLK), // 1-bit Clock Input.CSB(CSB), // 1-bit Active-Low ICAP Enable.I(I),// 32-bit Configuration data input bus.RDWRB(RDWRB) // 1-bit Read/Write Select);// End of ICAP_VIRTEX6_inst instantiation// Specifies the input and output data width to be used with the// ICAP_VIRTEX6.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 163