Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsRAM_MODE => "TDP",-- SDP or TDPREAD_WIDTH_A => 0,-- 0, 1, 2, 4, 9, 18, or-- 36READ_WIDTH_B => 0, -- 0, 1, 2, 4, 9, 18RSTREG_PRIORITY_A => "RSTREG",-- RSTREG or REGCERSTREG_PRIORITY_B => "RSTREG",-- RSTREG or REGCESIM_COLLISION_CHECK => "ALL",-- Collision check-- enable "ALL",-- "WARNING_ONLY",-- "GENERATE_X_ONLY" or-- "NONE"SRVAL_A => X"0000000",-- Set/Reset value for A-- port outputSRVAL_B => X"0000000",-- Set/Reset value for B-- port outputWRITE_WIDTH_A => 0, -- 0, 1, 2, 4, 9, or 18WRITE_WIDTH_B => 0,-- 0, 1, 2, 4, 9, 18, or-- 36-- WriteMode: Specifies output behavior of the port being written to: "WRITE_FIRST" = written value-- appears on output port of the RAM "READ_FIRST" = previous RAM contents for that memory location appear-- on the output port "NO_CHANGE" = previous value on the output port remains the same. Default is-- WRITE_FIRST in TDP mode. Must equal READ_FIRST in SDP mode.WRITE_MODE_A => "WRITE_FIRST",WRITE_MODE_B => "WRITE_FIRST")port map (DOADO => DOADO,-- 16-bit A port data/LSB data outputDOBDO => DOBDO,-- 16-bit B port data/MSB data outputDOPADOP => DOPADOP,-- 2-bit A port parity/LSB parity outputDOPBDOP => DOPBDOP,-- 2-bit B port parity/MSB parity outputADDRARDADDR => ADDRARDADDR, -- 14-bit A port address/Read address inputADDRBWRADDR => ADDRBWRADDR, -- 14-bit B port address/Write address inputCLKARDCLK => CLKARDCLK,-- 1-bit A port clock/Read clock inputCLKBWRCLK => CLKBWRCLK,-- 1-bit B port clock/Write clock inputDIADI => DIADI,-- 16-bit A port data/LSB data inputDIBDI => DIBDI,-- 16-bit B port data/MSB data inputDIPADIP => DIPADIP,-- 2-bit A port parity/LSB parity inputDIPBDIP => DIPBDIP,-- 2-bit B port parity/MSB parity inputENARDEN => ENARDEN,-- 1-bit A port enable/Read enable inputENBWREN => ENBWREN,-- 1-bit B port enable/Write enable inputREGCEAREGCE => REGCEAREGCE, -- 1-bit A port register enable/Register enable inputREGCEB => REGCEB,-- 1-bit B port register enable inputRSTRAMARSTRAM => RSTRAMARSTRAM, -- 1-bit A port set/reset inputRSTRAMB => RSTRAMB,-- 1-bit B port set/reset inputRSTREGARSTREG => RSTREGARSTREG, -- 1-bit A port register set/reset inputRSTREGB => RSTREGB,-- 1-bit B port register set/reset inputWEA => WEA,-- 2-bit A port write enable inputWEBWE => WEBWE-- 4-bit B port write enable/Write enable input);-- End of RAMB18E1_inst instantiation-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"-- "WRITE_FIRST",-- "READ_FIRST", or-- "NO_CHANGE"Verilog Instantiation Template// RAMB18E1: 18K-bit Configurable Synchronous Block RAM// Virtex-6// Xilinx HDL Language Template, version 11.1RAMB18E1 #(.DOA_REG(0),.DOB_REG(0),// Optional output// register on A port// (0 or 1)// Optional output// register on B port// (0 or 1)// INITP_00 to INITP_07: Allows specification of the initial contents of the 2KB parity data memory// array..INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),Virtex-6 Libraries Guide for HDL Designs286 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design Elements.INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000),// INIT_00 to INIT_3F: Allows specification of the initial contents of the 16KB data memory array..INIT_00(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_01(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_02(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_03(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_04(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_05(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_06(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_07(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_08(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_09(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_10(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_11(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_12(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_13(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_14(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_15(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_16(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_17(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_18(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_19(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_20(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_21(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_22(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_23(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_24(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_25(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_26(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_27(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_28(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_29(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_30(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_31(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_32(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_33(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_34(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_35(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_36(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_37(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_38(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_39(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3A(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3B(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3C(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3D(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3E(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3F(256’h0000000000000000000000000000000000000000000000000000000000000000),.INIT_A(18’h00000),// Initial values on AVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 287
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Virtex-6 Libraries Guide forHDL Des
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Table of ContentsXilinx Trademarks
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Available Attributes ..............
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Port Descriptions..................
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For More Information...............
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ODDR...............................
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Design Entry Method ...............
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Chapter 1About this GuideThis HDL g
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Chapter 2About UnimacrosThis sectio
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Chapter 2: About UnimacrosName Dire
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Chapter 2: About UnimacrosVHDL Inst
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Chapter 2: About UnimacrosINIT_76 =
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Chapter 2: About Unimacros.INIT_50(
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Chapter 2: About UnimacrosBRAM_SING
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Chapter 2: About UnimacrosWRITE_WID
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Chapter 2: About UnimacrosBRAM_SIZE
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Chapter 2: About UnimacrosINITP_02
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Chapter 3Functional CategoriesThis
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Chapter 3: Functional CategoriesCon
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Chapter 4About Design ElementsThis
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