Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 3: Functional CategoriesConvenience PrimitivesDesign ElementBUFGBUFGCEDescriptionConvenience Primitive: Global Clock BufferConvenience Primitive: Global Clock Buffer with Clock EnableBUFGCE_1 Convenience Primitive: Global Clock Buffer with Clock Enable and Output State 1BUFGMUXConvenience Primitive: Global Clock MUX BufferBUFGMUX_1 Convenience Primitive: Global Clock MUX Buffer with Output State 1BUFGMUX_CTRLBUFGPBUFHMMCM_BASEConvenience Primitive: 2-to-1 Global Clock MUX BufferConvenience Primitive: Primary Global Buffer for Driving Clocks or LonglinesConvenience Primitive: Clock buffer for a single clocking regionConvenience Primitive: Mixed signal block designed to support clock network deskew,frequency synthesis, and jitter reduction.Gigabit I/ODesign ElementGTHE1_QUADGTXE1DescriptionPrimitive: Gigabit TransceiverPrimitive: Gigabit TransceiverI/O ComponentsDesign ElementDCIRESETIBUFIBUFDSIBUFGIBUFGDSIOBUFIOBUFDSIODELAYE1ISERDESE1KEEPEROBUFOBUFDSOBUFTDSOSERDESE1PULLDOWNPULLUPDescriptionPrimitive: DCI State Machine Reset (After Configuration Has Been Completed)Primitive: Input BufferPrimitive: Differential Signaling Input BufferPrimitive: Dedicated Input Clock BufferPrimitive: Differential Signaling Dedicated Input Clock Buffer and Optional DelayPrimitive: Bi-Directional BufferPrimitive: 3-State Differential Signaling I/O Buffer with Active Low Output EnablePrimitive: Input and Output Fixed or Variable Delay ElementPrimitive: Input SERial/DESerializerPrimitive: KEEPER SymbolPrimitive: Output BufferPrimitive: Differential Signaling Output BufferPrimitive: 3-State Output Buffer with Differential Signaling, Active-Low OutputEnablePrimitive: Dedicated IOB Output SerializerPrimitive: Resistor to GND for Input Pads, Open-Drain, and 3-State OutputsPrimitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State OutputsVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 77