Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsBUFGPConvenience Primitive: Primary Global Buffer for Driving Clocks or LonglinesIntroductionThis design element is a primary global buffer that is used to distribute high fan-out clock or control signalsthroughout in FPGA devices. It is equivalent to an IBUFG driving a BUFG.This design element provides direct access to Configurable Logic Block (CLB) and Input Output Block (IOB)clock pins and limited access to other CLB inputs. The input to a BUFGP comes only from a dedicated IOB.Because of its structure, this element can always access a clock pin directly. However, it can access only oneof the F3, G1, C3, or C1 pins, depending on the corner in which the BUFGP is placed. When the required pincannot be accessed directly from the vertical line, PAR feeds the signal through another CLB and uses generalpurpose routing to access the load pin.Design Entry MethodThis design element is only for use in schematics.For More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs100 www.xilinx.com UG623 (v 11.4) December 2, 2009