Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs172 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design ElementsIOBUFDSPrimitive: 3-State Differential Signaling I/O Buffer with Active Low Output EnableIntroductionThe design element is a bidirectional buffer that supports low-voltage, differential signaling. For the IOBUFDS, adesign level interface signal is represented as two distinct ports (IO and IOB), one deemed the "master" andthe other the "slave." The master and the slave are opposite phases of the same logical signal (for example,MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to helpimprove signal integrity and reduce external components. Also available is a programmable delay is to assist inthe capturing of incoming data to the device.Logic TableInputs Bidirectional OutputsI T IO IOB OX 1 Z Z No Change0 0 0 1 0I 0 1 0 1Port DescriptionsPort Direction Width FunctionO Output 1 Buffer outputIO Inout 1 Diff_p inoutIOB Inout 1 Diff_n inoutI Input 1 Buffer inputT Input 1 3-state enable inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 173
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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