Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsRAM32X1SPrimitive: 32-Deep by 1-Wide Static Synchronous RAMIntroductionThe design element is a 32-word by 1-bit static random access memory with synchronous write capability. Whenthe write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D) into theword selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However, (WCLK)can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM32X1S during configuration using the INIT attribute.Logic TableInputsWE (Mode) WCLK D OOutputs0 (read) X X Data1 (read) 0 X Data1 (read) 1 X Data1 (write) ↓ D D1 (read) ↑ X DataDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionsINIT Hexadecimal Any 32-Bit Value All zeros Specifies initial contents of the RAM.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 269