Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// ISERDESE1: (Input SERial/DESerializer)// Virtex-6// Xilinx HDL Language Template, version 11.1ISERDESE1 #(.DATA_RATE("DDR"),// Single Data Rate or Double Data Rate operation..DATA_WIDTH(4),// Parallel data width selection..DYN_CLKDIV_INV_EN("FALSE"), // Enables dynamic CLKDIV inversion for Memory interfaces when TRUE..DYN_CLK_INV_EN("FALSE"), // Enables dynamic CLK inversion for Memory interfaces when TRUE..INIT_Q1(1’b0),// Defines the initial value of Q1 output..INIT_Q2(1’b0),// Defines the initial value of Q2 output..INIT_Q3(1’b0),// Defines the initial value of Q3 output..INIT_Q4(1’b0),// Defines the initial value of Q4 output..INTERFACE_TYPE("MEMORY"), // Memory or Networking interface type..IOBDELAY("NONE"),.NUM_CE(2),// Specifies the number of clock enables used for the ISERDES_NODELAY..OFB_USED("FALSE"),// Will select the sneak path from the OLOGIC, OSERDES..SERDES_MODE("MASTER"), // Specify whether the ISERDES is operating in master or slave modes when// cascaded width expansion..SRVAL_Q1(1’b0),// Defines the value of Q1 output when the SR is invoked..SRVAL_Q2(1’b0),// Defines the value of Q2 output when the SR is invoked..SRVAL_Q3(1’b0),// Defines the value of Q3 output when the SR is invoked..SRVAL_Q4(1’b0)// Defines the value of Q4 output when the SR is invoked.)ISERDESE1_inst (.O(O),// 1-bit Combinatorial output.// Q1 - Q6: 1-bit (each) Registered parallelized input data..Q1(Q1),.Q2(Q2),.Q3(Q3),.Q4(Q4),.Q5(Q5),.Q6(Q6),// SHIFTOUT1/SHIFTOUT2: 1-bit (each) If ISERDES_MODE="MASTER" and two ISERDES_NODELAY are to be cascaded,// connect to the slave ISERDES_NODELAY IDATASHIFTIN1/2 inputs..SHIFTOUT1(SHIFTOUT1),.SHIFTOUT2(SHIFTOUT2),.BITSLIP(BITSLIP),// 1-bit Input data bitslip function enable..CE1(CE1),// 1-bit Input data register clock enables..CE2(CE2),// 1-bit DITTO.CLK(CLK),// 1-bit Primary clock input pin used..CLKB(CLKB),// 1-bit Secondary clock input. If using in single clock DDR mode// (DATA_RATE="DDR"), invert the clock connected to the CLK pin and connect// to the CLKB pin. If using in dual clock mode DDR mode, connect a unique,// phase shifted clock to the CLKB pin. If using in single data-rate mode// (DATA_RATE="SDR"), leave this pin unconnected or connect to ground..CLKDIV(CLKDIV),.D(D),// 1-bit Divided clock to be used for parallelized data.// 1-bit Input data to be connected directly to the top-level input or I/O// port of the design or to an IODELAY component if additional input delay// control is desired.);.DDLY(DDLY),.DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit Dynamically select CLKDIV or CLKDIV_B (via an optional inversion)..DYNCLKSEL(DYNCLKSEL), // 1-bit Dynamically select CLK or CLK_B (via an optional inversion)..OCLK(OCLK),// 1-bit High speed output clock typically used for memory interfaces..OFB(OFB),// 1-bit Feedback Path from the OLOGIC/OSERDES Output (w/ or w/o ODELAY)..RST(RST),// 1-bit Active high asynchronous reset signal for the registers of the// SERDES.// SHIFTIN1/SHIFTIN2: 1-bit (each) If ISERDES_MODE="SLAVE" connect to the master ISERDES_NODELAY// IDATASHIFTOUT1/2 outputs. This pin must be grounded..SHIFTIN1(SHIFTIN1),.SHIFTIN2(SHIFTIN2)// End of ISERDESE1_inst instantiationVirtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 183