Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 4: About Design ElementsSTARTUP_VIRTEX6Primitive: Virtex®-6 Configuration Start-Up Sequence InterfaceIntroductionThis design element is used to interface device pins and logic to the Global Set/Reset (GSR) signal, the GlobalTristate (GTS) dedicated routing, the internal configuration signals, or the input pins for the SPI PROM ifan SPI PROM is used to configure the device. This primitive can also be used to specify a different clock forthe device startup sequence at the End of Configuring of the device, and to access the configuration clock tothe internal logic.Virtex-6 Libraries Guide for HDL Designs308 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 4: About Design ElementsPort DescriptionsPort Type Width FunctionCFGCLK Output 1 Configuration main clock output.CFGMCLK Output 1 Configuration internal oscillator clock output.CLK Input 1 User startup clock.DINSPI Output 1 Internal access to the DIN configuration pin when usingSPI PROM configurationEOS Output 1 Active High signal indicates the End Of Configuration.GSR Input 1 Active High Global Set/Reset (GSR) signal.GTS Input 1 Active High Global Tristate (GTS) signal.KEYCLEARB Input 1 Clear AES Decrypter Key from Battery-Backed RAM(BBRAM). To erase the battery-backed-RAM contents, pullKEYCLEARB Low for more than ~200ns.PACK Input 1 PROGRAM acknowledge.PREQ Output 1 PROGRAM request to fabricTCKSPI Output 1 Internal access to the TCK configuration pin when usingSPI PROM configuration.USRCCLKO Input 1 Internal user CCLK.USRCCLKTS Input 1 Internal user CCLK tristate enable.USRDONEO Input 1 Internal user DONE pin output controlUSRDONETS Input 1 User DONE tristate enableDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoIf the dedicated global tristate is to be used, connect the appropriate sourcing pin or logic to the GTS input pin ofthe primitive. To specify a clock for the startup sequence of configuration, connect a clock from the design to theCLK pin of this design element. CFGMCLK and CFGCLK allow access to the internal configuration clocks, whileEOS signals the end of the configuration startup sequence.If you are configuring the device using a SPI PROM, and access to the SPI PROM is necessary after configuration,use the TCK_SPI and DIN_SPI pins of the component to gain access to the otherwise dedicated configurationinput pins.Available AttributesAttribute Type Allowed Values Default DescriptionPROG_USR Boolean FALSE, TRUE FALSE Activate program event security featureCFGCLK_EN Boolean FALSE, TRUE FALSE Enables the Configuration logic main clock.CFGMCLK_EN Boolean FALSE, TRUE FALSE Enables the Configuration internal oscillatorclock .Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 309
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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