Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAttribute Type Allowed Values Default DescriptionSRVAL_BHexadecimalWRITEMODE String “WRITE_FIRST”,“READ_FIRST”,“NO_CHANGE”,Any 36 bit Value All zeros Specifies the output value of the RAMupon assertion of the synchronous reset(RSTREG) signal. Applies to port B inTDP mode and upper bits (includingparity bits) in SDP mode.“WRITE_FIRST”Specifies output behavior of the portbeing written to:• WRITE_FIRST - written valueappears on output port of the RAM• READ_FIRST - previous RAMcontents for that memory locationappear on the output port• NO_CHANGE - previous value onthe output port remains the same.Default is WRITE_FIRST in TDP mode.Must equal READ_FIRST in SDP mode.WRITE_WIDTH_A Integer 0, 1, 2, 4, 9, 18, 36 0 Specifies the desired data width for awrite to Port A including parity bits. Thisvalue must be 0 if the port is not used.Otherwise should be set to the desiredwrite width. Not used in SDP mode.WRITE_WIDTH_B Integer 0, 1, 2, 4, 9, 18, 36,720 Specifies the desired data width for awrite to Port B including parity bits. Thisvalue must be 0 if the port is not used.Otherwise should be set to the desiredwrite width. In SDP mode, this is thewrite width including parity bits.VHDL Instantiation Template-- RAMB36E1: 36K-bit Configurable Synchronous Block RAM-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2RAMB36E1_inst : RAMB36E1generic map (DOA_REG => 0,DOB_REG => 0,EN_ECC_READ => FALSE,EN_ECC_WRITE => FALSE,-- Optional output-- register on A port (0-- or 1)-- Optional output-- register on B port (0-- or 1)-- Enable ECC decoder,-- TRUE or FALSE-- Enable ECC encoder,-- TRUE or FALSE-- INITP_00 to INITP_0F: Allows specification of the initial contents of the 4KB parity data memory-- array.INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",Virtex-6 Libraries Guide for HDL Designs294 www.xilinx.com UG623 (v 11.4) December 2, 2009