Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAttribute Type Allowed_ValuesDefault DescriptionINIT_46INIT_47INIT_48INIT_49INIT_4AINIT_4BINIT_4CINIT_4DINIT_4EINIT_4FINIT_50INIT_51INIT_52INIT_53INIT_54INIT_55INIT_56INIT_57HexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimalHexadecimal16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffff16’h0000 to16’hffffSIM_DEVICE String “VIRTEX5”,”VIRTEX6”16’h0000 Test register 316’h0000 Test register 416’h0000 Sequence register 016’h0000 Sequence register 116’h0000 Sequence register 216’h0000 Sequence register 316’h0000 Sequence register 416’h0000 Sequence register 516’h0000 Sequence register 616’h0000 Sequence register 716’h0000 Alarm limit register 016’h0000 Alarm limit register 116’h0000 Alarm limit register 216’h0000 Alarm limit register 316’h0000 Alarm limit register 416’h0000 Alarm limit register 516’h0000 Alarm limit register 616’h0000 Alarm limit register 7“VIRTEX5”Allows the simulation model to reflect thereduction of the minimum divide ratio betweenthe DRP clock (DCLK) and the lower frequencyADC clock (ADCCLOCK) from 8 to 2.SIM_MONITOR_FILE String 0 bit String design.txt Simulation analog entry fileVirtex-6 Libraries Guide for HDL Designs314 www.xilinx.com UG623 (v 11.4) December 2, 2009