Xilinx Virtex-6 Libraries Guide for HDL Designs

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Chapter 2: About UnimacrosWRITE_WIDTH_A/B-DIA/DIB2118-109 - 54 - 321READ_WIDTH_A/B-DOA/DOB BRAM_SIZE ADDRA/B WEA/B36-19 36Kb1418-10 149 - 5 144 - 3 142 14136-19 36Kb1518-10 159 - 5 154 - 3 152 15118-10 18Kb109 - 5 114 - 3 122 13118-10 18Kb119 - 5 114 - 3 122 13118-10 18Kb129 - 5 124 - 3 122 13118-10 18Kb139 - 5 134 - 3 132 13118-10 18Kb149 - 5 144 - 3 142 1411 1 Cascade 16 1151514141414141121111Virtex-6 Libraries Guide for HDL Designs38 www.xilinx.com UG623 (v 11.4) December 2, 2009
Chapter 2: About UnimacrosDesign Entry MethodThis unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the ConfigurationTable above to correctly configure it to meet your design needs.InstantiationInferenceCORE Generator and wizardsMacro supportYesNoNoRecommendedAvailable AttributesAttribute(s) Type Allowed Values Default DescriptionBRAM_SIZE String “18Kb”, “36Kb” “18Kb” Configures RAM as 18Kb or 36Kb memory.DO_REG Integer 0, 1 0 A value of 1 enables to the output registers tothe RAM enabling quicker clock-to-out fromthe RAM at the expense of an added clock cycleof read latency. A value of 0 allows a read inone clock cycle but will have slower clock to outtiming.INITAny 72-Bit Value All zeros Specifies the initial value on the output afterconfiguration.INIT_FILE String 0 bit string “NONE” Name of file containing initial values.READ_WIDTH,WRITE_WIDTHSIM_COLLISION_CHECKInteger 1 - 72 36 Specifies size of DI/DO bus. READ_WIDTH andWRITE_WIDTH must be equal.String“ALL,”"WARNING_ONLY","GENERATE_X_ONLY","NONE”“ALL”Allows modification of the simulation behavior ifa memory collision occurs. The output is affectedas follows:• "ALL" - Warning produced and affectedoutputs/memory location go unknown (X).• "WARNING_ONLY" - Warning producedand affected outputs/memory retain lastvalue.• "GENERATE_X_ONLY" - No warning.However, affected outputs/memory gounknown (X).• "NONE" - No warning and affectedoutputs/memory retain last value.Note Setting this to a value other than "ALL"can allow problems in the design go unnoticedduring simulation. Care should be taken whenchanging the value of this attribute. Please seethe Synthesis and Simulation Design Guide for moreinformation.SIM_MODE String "SAFE", "FAST" . "SAFE" This is a simulation only attribute. Itwill direct the simulation model to run inperformance-oriented mode when set to "FAST."Please see the Synthesis and Simulation DesignGuide for more information.SRVAL A, SRVAL_BHexadecimalHexadecimalAny 72-Bit Value All zeroes Specifies the output value of on the DO portupon the assertion of the synchronous reset (RST)signal.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 39
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Xilinx Virtex-6 Libraries Guide for HDL Designs

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