Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsAvailable AttributesAttribute Type Allowed Values Default DescriptionINIT Hexadecimal Any 256-Bit Value AllzerosSpecifies the initial contents of the RAM.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read-- single-port distributed LUT RAM-- Virtex-5/6, Spartan-6-- Xilinx HDL Libraries Guide, version 11.2RAM256X1S_inst : RAM256X1Sgeneric map (INIT => X"0000000000000000000000000000000000000000000000000000000000000000")port map (O => O, -- Read/Write port 1-bit ouputA => A, -- Read/Write port 8-bit address inputD => D, -- RAM data inputWCLK => WCLK, -- Write clock inputWE => WE -- Write enable input);-- End of RAM256X1S_inst instantiationVerilog Instantiation Template// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read// single-port distributed LUT RAM// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2RAM256X1S #(.INIT(256’h0000000000000000000000000000000000000000000000000000000000000000)) RAM256X1S_inst (.O(O), // Read/Write port 1-bit output.A(A), // Read/Write port 8-bit address input.WE(WE), // Write enable input.WCLK(WCLK), // Write clock input.D(D) // RAM data input);// End of RAM256X1S_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL Designs264 www.xilinx.com UG623 (v 11.4) December 2, 2009