Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsIBUFGPrimitive: Dedicated Input Clock BufferIntroductionThe IBUFG is a dedicated input to the device which should be used to connect incoming clocks to the FPGA’sglobal clock routing resources. The IBUFG provides dedicated connections from a top level port to the MMCMor BUFG providing the minimum amount of clock delay and jitter to the device. The IBUFG input can only bedriven by the clock capable (CC) or global clock (GC) pins.Port DescriptionsPort Direction Width FunctionO Output 1 Clock Buffer outputI Input 1 Clock Buffer inputDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportYesRecommendedNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionIOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.VHDL Instantiation TemplateUnless they already exist, copy the following two statements and paste them before the entity declaration.Library UNISIM;use UNISIM.vcomponents.all;-- IBUFG: Global Clock Buffer (sourced by an external pin)-- Xilinx HDL Libraries Guide, version 11.2IBUFG_inst : IBUFGgeneric map (IOSTANDARD => "DEFAULT")port map (O => O, -- Clock buffer outputI => I -- Clock buffer input (connect directly to top-level port));-- End of IBUFG_inst instantiationVirtex-6 Libraries Guide for HDL Designs158 www.xilinx.com UG623 (v 11.4) December 2, 2009