Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsEFUSE_USRPrimitive: 32-bit non-volatile design IDIntroductionUse this element to internally access 32 non-volatile fuses that can store bits specific to the design (e.g. a uniqueID associated with each design). These efuses must be externally written through JTAG.Port DescriptionsPort Type Width FunctionEFUSEUSR[31:0] Output 32 User E-Fuse register valueDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoAvailable AttributesAttribute Type Allowed Values Default DescriptionSIM_EFUSE_VALUE Hexadecimal 32’h00000000 to32’hffffffff32’h00000000 Causes simulation model to drive astatic value onto these pins after INITgoes high.VHDL Instantiation Template-- EFUSE_USR: 32-bit non-volatile design ID-- Virtex-6-- Xilinx HDL Libraries Guide, version 11.2EFUSE_USR_inst : EFUSE_USRgeneric map (SIM_EFUSE_VALUE => X"00000000")port map (EFUSEUSR => EFUSEUSR);-- End of EFUSE_USR_inst instantiation-- Causes simulation model to drive a static value onto these pins after-- INIT goes high.-- 32-bit User E-Fuse register valueVirtex-6 Libraries Guide for HDL Designs130 www.xilinx.com UG623 (v 11.4) December 2, 2009