Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsCAPTURE_VIRTEX6Primitive: Virtex®-6 Readback Register Capture ControlIntroductionThis element provides user control and synchronization over when and how the capture register (flip-flop andlatch) information task is requested. The readback function is provided through dedicated configuration portinstructions. However, without this element, the readback data is synchronized to the configuration clock.Only register (flip-flop and latch) states can be captured. Although LUT RAM, SRL, and block RAM statesare readback, they cannot be captured.An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-Highclock transition. By default, data is captured after every trigger when transition on CLK while CAP is asserted.To limit the readback operation to a single data capture, add the ONESHOT=TRUE attribute to this element.Port DescriptionsPort Direction Width FunctionCAP Input 1 Readback capture triggerCLK Input 1 Readback capture clockDesign Entry MethodInstantiationInferenceCORE Generator and wizardsMacro supportRecommendedNoNoNoConnect all inputs and outputs to the design in order to ensure proper operation.Available AttributesAttribute Type Allowed Values Default DescriptionONESHOT Boolean TRUE, FALSE TRUE Specifies the procedure for performing single readback perCAP trigger.Virtex-6 Libraries Guide for HDL Designs110 www.xilinx.com UG623 (v 11.4) December 2, 2009