Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsISERDESE1Primitive: Input SERial/DESerializerIntroductionThis design element is a dedicated serial-to-parallel converter with specific clocking and logic features designedto facilitate the implementation of high-speed source-synchronous applications. It avoids the additional timingcomplexities encountered when designing deserializers in the FPGA fabric.Port DescriptionsPort Type Width FunctionBITSLIP Input 1 Input data bitslip function enable.CE1 Input 1 Input data register clock enables.CE2 Input 1 Input data register clock enables.CLK Input 1 Primary clock input pin used.CLKB Input 1 Secondary clock input.• If using in single clock DDR mode (DATA_RATE="DDR"),invert the clock connected to the CLK pin and connect to theCLKB pin.• If using in dual clock mode DDR mode, connect a unique,phase shifted clock to the CLKB pin.Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 179