Xilinx Virtex-6 Libraries Guide for HDL Designs

Chapter 4: About Design ElementsVerilog Instantiation Template// SRLC32E: 32-bit variable length shift register LUT// with clock enable// Virtex-5, Virtex-6, Spartan-6// Xilinx HDL Libraries Guide, version 11.2SRLC32E #(.INIT(32’h00000000) // Initial Value of Shift Register) SRLC32E_inst (.Q(Q), // SRL data output.Q31(Q31), // SRL cascade output pin.A(A), // 5-bit shift depth select input.CE(CE), // Clock enable input.CLK(CLK), // Clock input.D(D) // SRL data input);// End of SRLC32E_inst instantiationFor More InformationSee the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).Virtex-6 Libraries Guide for HDL DesignsUG623 (v 11.4) December 2, 2009 www.xilinx.com 307